`timescale 100ns / 100ps

                       
module tb_crc32_d8
    (   
        output logic                    clk
    );
//*********************** КОНСТАНТЫ ****************************************************************

//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic reset_n;

    logic [3:0][7:0]    crc;
    logic [7:0]         data;
    
    logic               crc_init;
    logic               wre;

//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************


//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************

    crc32_d8
    crc32_d8_inst1
    (
        .init                   (crc_init),
        .clk                    (clk),
        
        .data                   (data), 
        .wre                    (wre),
        
        .crc                    (crc)
    );
  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25  reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin        // CLK
        
        crc_init    = 0;
        data        = 0;
        wre         = 0;
        #1;
        
        
        crc_init    = 1;
        @(posedge clk);
        crc_init    = 0;
        wre         = 1;
        data        = 8'hff;
        repeat (6)
            @(posedge clk);
        
        data        = 8'hD4;
        @(posedge clk);
        data        = 8'h3D;
        @(posedge clk);
        data        = 8'h7E;
        @(posedge clk);
        data        = 8'h38;
        @(posedge clk);
        data        = 8'h00;
        @(posedge clk);
        data        = 8'h95;
        @(posedge clk);
            data        = 8'h08;
        @(posedge clk);
            data        = 8'h06;
        @(posedge clk);
        wre         = 0;
    end    
endmodule